| 基于SystemVerilog的SRAM控制器IP核验证 |
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| 引用本文： | 金志威,周德新,王鹏,赵学娟. 基于SystemVerilog的SRAM控制器IP核验证[J]. 电子器件, 2012, 35(5): 619-622 |
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| 作者姓名： | 金志威 周德新 王鹏 赵学娟 |
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| 作者单位： | 中国民航大学航空自动化学院;中国民航大学天津市民用航空器适航与维修重点实验室 |
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| 基金项目： | 国家自然科学基金项目(61179044);中国民航大学校级重点科研项目(CAUC2009ZD0102);中央高校基本科研业务费项目(ZXH2009A001) |
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| 摘 要： | 随着硬件设计复杂度的提高,设计的后期验证在设计生命周期中占据的比重也越来越大。能否对设计进行全面有效的验证,是验证人员所面临的主要问题。采用SystemVerilog语言对SRAM控制器IP核搭建验证环境,并结合SVA断言技术对其实行监控,得出代码及功能覆盖率数据。通过与传统的验证方法对比分析可知,基于SystemVerilog的验证方法更加全面有效,提高了验证质量。
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| 关 键 词： | 验证 System Verilog 覆盖率 SVA |
Verification of SRAM Controller IP Core Based SystemVerilog |
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| ZHOU Dexin,JIN Zhiwei,WANG Peng,ZHAO Xuejuan. Verification of SRAM Controller IP Core Based SystemVerilog[J]. Journal of Electron Devices, 2012, 35(5): 619-622 |
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| Authors: | ZHOU Dexin JIN Zhiwei WANG Peng ZHAO Xuejuan |
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| Affiliation: | 1.Aeronautical Automation College,Civil Aviation University of China,Tianjin 300300,China; 2.Tianjin Key Laboratory for Civil Aircraft Airworthiness and Maintenance,Tianjin 300300,China) |
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| Abstract: | With the improvement of the complexity of the hardware design,the design of the verification is taking up more and more proportion in the design life cycle.It is the main problem faced by the verification engineers to give a comprehensive and efficient verification.The SRAM controller IP core is verified by the SystemVerilog verification environment,and monitored by SystemVerilog assertion technology to get the code and functional coverage data.After comparing and analyzing,the verification method based SystemVerilog is more comprehensive and more efficient than the traditional verification method,so that it improves the quality of verification. |
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| Keywords: | verification SystemVerilog coverage SVA |
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