A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration |
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Authors: | Changsik Yoo Kye-Hyun Kyung Kyunam Lim Hi-Choon Lee Joon-Wan Chai Nak-Won Heo Dong-Jin Lee Chang-Hyun Kim |
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Affiliation: | Div. of Electr. & Comput. Eng., Hanyang Univ., Seoul, South Korea; |
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Abstract: | A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation. |
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