| 基于芯核分层布图的3D芯片扫描链优化设计 |
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| 引用本文： | 王伟,朱侠,方芳,秦振陆,郭二辉,任福继.基于芯核分层布图的3D芯片扫描链优化设计[J].电子测量与仪器学报,2016,30(10):1482-1489. |
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| 作者姓名： | 王伟 朱侠 方芳 秦振陆 郭二辉 任福继 |
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| 作者单位： | 1. 合肥工业大学计算机与信息学院 合肥230009;合肥工业大学情感计算与先进智能机器安徽省重点实验室 合肥230009;2. 合肥工业大学计算机与信息学院 合肥230009;3. 中国电子科技集团第三十八研究所 合肥230009 |
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| 基金项目： | 国家自然科学基金重点项目(61432004)，国家自然科学基金(61474035;61306049)，安徽省科技攻关项目(1206c0805039)，安徽省自然科学基金(1508085QF129)，教育部新教师基金(20130111120030) |
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| 摘 要： | 随着3D堆叠技术的不断发展,芯片测试已成为一大研究热点。为了减少三维堆叠集成电路(three dimensional stacked integrated circuits,3D-SICs)绑定前和绑定中的总测试时间,提出了基于芯核分层布图的改进模拟退火算法和扫描链分配算法,通过将芯核均匀地分配到各层上实现对各层电路中芯核合理化地布图,再利用"绑定中测试"复用"绑定前测试"扫描链的方式,协同优化绑定前和绑定中的总测试时间和硬件开销。在ITC’02基准电路上的实验结果表明,本文方法在TSV数量的约束下,测试时间和硬件开销分别最高降低了27.26%和89.70%,且各层芯核布图更加均匀。
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| 关 键 词： | 芯核分层布图 绑定前测试 绑定中测试 协同优化 扫描链均衡 硬件开销 |
Optimal design of 3D chip scan chains based on cores hierarchical placement |
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| Wang Wei,Zhu Xi,Fang Fang,Qin Zhenlu,Guo Erhui and Ren Fuji.Optimal design of 3D chip scan chains based on cores hierarchical placement[J].Journal of Electronic Measurement and Instrument,2016,30(10):1482-1489. |
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| Authors: | Wang Wei Zhu Xi Fang Fang Qin Zhenlu Guo Erhui and Ren Fuji |
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| Affiliation: | 1. Hefei University of Technology, Hefei 230009, China; 2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei 230009, China,1. Hefei University of Technology, Hefei 230009, China; 2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei 230009, China,Hefei University of Technology, Hefei 230009, China,1. Hefei University of Technology, Hefei 230009, China; 2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei 230009, China,No.38 Research Institute of China Electronics Technology Group Corporation, Hefei 230009, China and 1. Hefei University of Technology, Hefei 230009, China; 2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei 230009, China |
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| Abstract: | |
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| Keywords: | cores-hierarchical-placement pre-bond test mid-bond test co-optimization scan chains balance hardware overhead |
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