基于FPGA内嵌DSP硬核的脉冲压缩设计与实现

在伪随机编码体制的超宽带雷达中，原始回波信号的实时脉冲压缩是信号处理的首要和关键步骤。由于超宽带雷达的采样率高、数据量大，而微处理器处理速度和DSP芯片运算能力有限，提出了一种基于 FPGA 内嵌DSP硬核的快速实时脉冲压缩方法。基于时间域的互相关算法，通过调用FPGA中的DSP硬核进行并行计算，并结合流水线模式，实现快速实时脉冲压缩。仿真与实验结果表明，本文的方法能很好地实现超宽带雷达原始回波信号的快速实时脉冲压缩。

Design and implementation of pulse compression based on DSPs embedded in FPGA

In the pseudo random coded ultra‐wideband radar system ,real‐time pulse compression of the raw echo signal is the first and key step for signal processing .A new method of fast and real‐time pulse compression is proposed in this paper as the sampling rata of ultra‐wideband radar is high and the amount of echo data is large ,but the processing speed of DSP chips and microprocessors is limited . In order to achieve fast and real‐time pulse compression , this method is based on the cross‐correlation algorithm on time domain by calling the DSPs embedded in FPGA in pipeline mode to parallel computing .The simulation and experimental results show that the proposed method can well realize the pulse compression for ultra‐wideband radar .