Corrugated Heterojunction Metal‐Oxide Thin‐Film Transistors with High Electron Mobility via Vertical Interface Manipulation |
| |
Authors: | Minuk Lee Jeong‐Wan Jo Yoon‐Jeong Kim Seungbeom Choi Sung Min Kwon Seong Pil Jeon Antonio Facchetti Yong‐Hoon Kim Sung Kyu Park |
| |
Affiliation: | 1. School of Electrical and Electronic Engineering, Chung‐Ang University, Seoul, Korea;2. SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon, Korea;3. Department of Chemistry and the Materials Research Center, Northwestern University, Evanston, IL, USA;4. Flexterra Corporation, Skokie, IL, USA;5. School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon, Korea |
| |
Abstract: | A new strategy is reported to achieve high‐mobility, low‐off‐current, and operationally stable solution‐processable metal‐oxide thin‐film transistors (TFTs) using a corrugated heterojunction channel structure. The corrugated heterojunction channel, having alternating thin‐indium‐tin‐zinc‐oxide (ITZO)/indium‐gallium‐zinc‐oxide (IGZO) and thick‐ITZO/IGZO film regions, enables the accumulated electron concentration to be tuned in the TFT off‐ and on‐states via charge modulation at the vertical regions of the heterojunction. The ITZO/IGZO TFTs with optimized corrugated structure exhibit a maximum field‐effect mobility >50 cm2 V?1 s?1 with an on/off current ratio of >108 and good operational stability (threshold voltage shift <1 V for a positive‐gate‐bias stress of 10 ks, without passivation). To exploit the underlying conduction mechanism of the corrugated heterojunction TFTs, a physical model is implemented by using a variety of chemical, structural, and electrical characterization tools and Technology Computer‐Aided Design simulations. The physical model reveals that efficient charge manipulation is possible via the corrugated structure, by inducing an extremely high carrier concentration at the nanoscale vertical channel regions, enabling low off‐currents and high on‐currents depending on the applied gate bias. |
| |
Keywords: | corrugated structures heterointerfaces metal‐oxide thin‐film transistors solution processes TCAD simulations |
|
|