| 一种10ps以下时钟偏差的纯数字电路分频器设计 |
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| 引用本文： | 段炼,方昊,王逵,帖猛,程旭.一种10ps以下时钟偏差的纯数字电路分频器设计[J].电路与系统学报,2009,14(6). |
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| 作者姓名： | 段炼 方昊 王逵 帖猛 程旭 |
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| 作者单位： | 北京大学,微处理器研发中心,北京,100871 |
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| 摘 要： | 本文对一款常用任意整数分频器进行改进,提出了一种纯数字、低时钟偏差、可获得任意整数分频结果的时钟分频器设计方案.该分频器由计数器与输出锁存器构成,通过调节逻辑结构与线延迟,完全平衡各时钟传播路径,大幅降低时钟偏差.仿真结果表明,在TSMC 0.13μm CMOS工艺下,当输入时钟频率在600MHz时,时钟偏差可控制在10ps以内.该分频器还包含自测电路,可判断时钟偏差是否满足要求.
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| 关 键 词： | 分频器 互补金属氧化物半导体 时钟偏差 |
A 10ps skew pure digital clock divider |
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| DUAN Lian,FANG Hao,WANG Kui,TIE Meng,CHENG Xu.A 10ps skew pure digital clock divider[J].Journal of Circuits and Systems,2009,14(6). |
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| Authors: | DUAN Lian FANG Hao WANG Kui TIE Meng CHENG Xu |
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| Affiliation: | DUAN Lian,FANG Hao,WANG Kui,TIE Meng,CHENG Xu ( Microprocessor Research , Development Center,School of EECS,Peking University,Beijing 100871,China ) |
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| Abstract: | A pure digital low-skew clock divider which can divide the master clock by any integer within 10ps skew is proposed. It is constructed by a counter and flip-flops, and is optimized by balancing all the possible clock paths to reduce the skew. The simulation results under TSMC 013μm CMOS technology show that the clock skew can be reduced below 10ps while working at 600MHz. Moreover, this clock divider also contains a self-testing circuit to confirm that the skew constraints are satisfied. |
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| Keywords: | clock Divider CMOS clock skew |
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