High-speed and low-power feRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme |
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| Authors: | Zhang G. Jia Z. Ren T. Chen H. |
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| Affiliation: | Inst. of Microelectron., Tsinghua Univ., Beijing; |
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| Abstract: | A novel design method for nonvolatile ferroelectric random access memory (FeRAM) using a merged bitline (BL)/plateline (PL) array architecture with a twin bitline-driven scheme is proposed. This method is effective in improving the FeRAM performance and reduces the power consumption. A 128 Kbit FeRAM prototype applying the proposed circuitry is implemented. The chip size, access time and memory array power dissipation are reduced to about 87, 44 and 15.8%, respectively, in comparison with those of conventional FeRAM. |
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