A vertical-junction field-effect transistor

A vertical JFET structure is described which allows realization of submicrometer channel-length devices using standard photolithographic techniques. The fabrication procedure utilizes an anisotropic etch followed by an impurity diffusion or implantation to define the channel. A numerical simulation of the JFET operation is implemented using a finite-element analysis technique. Typical devices exhibit high-output conductance and a tendency to resist channel pinchoff at the drain end. Etched bipolar transistors having current gains as high as 400 can also be formed concurrently with the fabrication of the vertical JFET structures.