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IRIG-B码的产生与解调系统设计与实现
引用本文:刘明波,耿文建,华安,刘艳.IRIG-B码的产生与解调系统设计与实现[J].国外电子测量技术,2010,29(5):47-51.
作者姓名:刘明波  耿文建  华安  刘艳
作者单位:1. 中国卫星海上测控部,无锡,214431
2. 西北师范大学教育技术与传播学院,兰州,730000
摘    要:给出了一种基于ISA总线的B码产生与解调系统设计的新方法。B码产生模块从某个时间初始值开始运行产生时间信息,并按照国际通用的B码格式,产生出与当前时间对应的B码信号,其中运行初始值可由微机通过ISA总线任意设置;B码解调模块将标准时统设备送来的B码信号,通过电平转换之后送入FPGA,由FPGA通过内部逻辑解调出8421码格式的天、时、分、秒信息,通过ISA总线送人微机,以校准本机的系统时间。本系统可用于时统设备的调试与检修,也可作为实践教学设备使用,使所属人员了解IRIG-B码的结构及工作流程。设计具有灵活性和开放性的特点。

关 键 词:FPGA  IRIG-B  ISA总线  产生  解调

Design and implement of IRIG-B builder and decoder
Liu Mingbo,Geng Wenjian,Hua An,Liu Yan.Design and implement of IRIG-B builder and decoder[J].Foreign Electronic Measurement Technology,2010,29(5):47-51.
Authors:Liu Mingbo  Geng Wenjian  Hua An  Liu Yan
Affiliation:Liu Mingbo Geng Wenjian Hua An Liu Yan (1. Chinese Satellite Marine Tracking and Commanding Center, Wuxi 214431, China; 2. Northwest Normal University, Lanzhou 730000, China)
Abstract:This article puts forward a new method of B-code generating and decoding basing on ISA bus. According to the international B-code format, B-Code generation part outputs B-code signal which is corresponding to current time which is generated form a pre-defined data through ISA bus. B-code decoding part brings the B-code signal into FPGA after voltage-level transferring, and then decodes it as 8421 format's day, hour, minute, second information, then send them to computer through ISA bus to adjust system time. This system can not only be applied to examine and repair time-unit system, but also be applied to teaching to help technician to understand the structure and flow of IRIG-B code. This design has the character of agility and opening.
Keywords:FPGA  IRIG-B
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