Bus-Switch Encoding for Power Optimization of Address Bus

This paper presents a novel encoding technique to minimize the switch activities on the highly capacitive memory address bus so as to reduce power dissipation of bus. This technique is based on the temporal locality and spatial locality of instruction address. The experimental results based on an instruction set simulator and SPEC2000 benchmarks show that the presented encoding technique can reduce signal transitions on the address bus by 83.8%, and the actual overhead of the encoder circuit is estimated after encoder has been designed and synthesized with 0.18-μm CMOS technology. The results show that our technique well outperforms specialized low-power encoding schemes presented in the past.

Bus-Switch Encoding for Power Optimization of Address Bus