Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.