Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.