Fabrication and electrical performance of high-density arrays of nanometric silicon tips

We propose and demonstrate a simple and low cost process for the fabrication of large area arrays of nanometric silicon tips, for use as Field Emission Devices (FEDs). The process combines Interference Lithography (IL) with isotropic Reactive Ion Etching (RIE). Si tips with typical curvature radius of 20 nm and height of 900 nm were recorded with a periodicity of 1 μm (density of 10⁶ tips/mm²) covering a Silicon wafer of 2 in. The measurement of the electrical performance of the arrays demonstrates the feasibility of the association of these two techniques for recording Field Emission Tips.