一种高性能并行计算架构的FPGA实现

针对传统的现场可编程门阵列（Field Programmable Gate Array,FPGA）开发方法效率低、不能充分利用芯片逻辑资源等问题，提出了一种高性能并行计算架构。设计了统一的软件、硬件编程模型，并提供FPGA操作系统层级的支持，将部分可重构技术应用于硬件线程的开发，使该架构具备资源管理和复用的能力。同时还设计了软件、硬件协同开发的流程。在开发板ZC702上进行了设计验证，评估了架构的额外资源消耗情况，并以排序算法为例展示了该架构多线程设计的灵活性。

FPGA implementation of a high performance parallel computing architecture

For the low efficiency and low logic resource utilization of traditional development methods for field programmable gate array(FPGA),a high performance parallel computing architecture is proposed.A unified software and hardware programming model is designed,and FPGA operating system level support is provided.Partial reconfigurable technology is applied to develop hardware threads,which enables the architecture to have the ability to manage and reuse resources.The process of software and hardware collaborative development is also designed.Design verification is performed on the development board ZC702.The additional resource consumption of the architecture is evaluated and the flexibility of multithreading is demonstrated using a sorting algorithm as an example.