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| 集成电路时间延迟优化分析与模拟 | |
| 引用本文： | 李文石,唐璞山,许杞安,章焱. 集成电路时间延迟优化分析与模拟[J]. 微电子学, 2004, 34(6): 655-657,662 |
| 作者姓名： | 李文石 唐璞山 许杞安 章焱 |
| 作者单位： | 1. 苏州大学,电子信息学院,微电子学系,江苏,苏州,215021 2. 复旦大学,微电子学系,上海,200433 3. 世宏科技(苏州)公司,器件实验室,江苏,苏州,215021 |
| 摘 要： | 基于Elmore模型，优化分析了N级二维CMOS传输门链和Ⅳ门三维双栅SOI IC的时间延迟，给出了HSPICE模拟结果。研完表明，由相同尺寸管子构成的N级二维CMOS门链，当把N级分作每3级为一组并且以缓冲门相间隔时，总时延存在极小值；由宽度尺寸比为3的三级不等尺寸管子所构造的传输门链间隔以缓冲门，也存在最小时延；当N门三维双栅SOI IC分为6个器件层时，可获得最小的时间延迟。 |
| 关 键 词： | Elmore模型 CMOS 传输门链 三维IC 时间延迟 HSPICE模拟 |
| 文章编号： | 1004-3365(2004)06-0655-03 |
Optimal Analysis and Simulation of Time Delay in Integrated Circuits |
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| LI Wen-shi,TANG Pu-shan,XU Qi-an,ZHANG Yan. Optimal Analysis and Simulation of Time Delay in Integrated Circuits[J]. Microelectronics, 2004, 34(6): 655-657,662 | |
| Authors: | LI Wen-shi TANG Pu-shan XU Qi-an ZHANG Yan |
| Affiliation: | LI Wen-shi~1,TANG Pu-shan~2,XU Qi-an~3,ZHANG Yan~1 |
| Abstract: | Time delay of N-stage CMOS transmission gate chain and N-gate 3D double-gate SOI IC is optimally analyzed based on Elmore model, and HSPICE simulation results are presented. The study has come to the following conclusions: 1) with each buffer inserted into every other three stages in the N-stage CMOS transmission gate chain, there is minimum delay time; 2) under the same condition as 1 and with N/PMOS device width ratio =3 in every 3-stage, there is also minimum delay time; 3) with m = 6 device-layers for for N-gate 3D DG SOI IC, there is minimum delay time. |
| Keywords: | Elmore model CMOS Transmission gate chain 3D IC Time delay HSPICE simulation |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |