Profiling interface traps in MOS transistors by the DCcurrent-voltage method |
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Authors: | Chih-Tang Sah Neugroschel A. Han K.M. Kavalieros J.T. |
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Affiliation: | Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL; |
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Abstract: | Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 1011 traps/cm2 generated by channel hot electron stress |
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