FPGAs achieve superior speed and density with antifuse advancements |
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| Affiliation: | 1. Department of Neurology, VU University Medical Center, Amsterdam, The Netherlands;2. Alzheimer Center and Department of Neurology, VU University Medical Center, Amsterdam, The Netherlands;3. Department of Clinical Neurophysiology and MEG Center, Neuroscience Campus Amsterdam, VU University Medical Center, Amsterdam, The Netherlands;4. Department of Psychiatry, BrainCenter Rudolf Magnus, University Medical Center Utrecht, Utrecht, The Netherlands;1. Machine Learning Group, Technische Universität Berlin, 10587 Berlin, Germany;2. BIFOLD – Berlin Institute for the Foundations of Learning and Data, Berlin, Germany;3. Department of Artificial Intelligence, Fraunhofer Heinrich Hertz Institute, 10587 Berlin, Germany;4. ISTD Pillar, Singapore University of Technology and Design, Singapore 487372, Singapore;5. Department of Informatics, University of Oslo, 0373 Oslo, Norway;6. Department of Artificial Intelligence, Korea University, Seoul 136–713, Korea;7. Max Planck Institut für Informatik, 66123 Saarbrücken, Germany;8. Aignostics GmbH, 10557 Berlin, Germany;9. Nota AI GmbH, 10117 Berlin, Germany |
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| Abstract: | FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs. |
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