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A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS
Authors:Khorram   S. Darabi   H. Zhimin Zhou Qiang Li Marholev   B. Chiu   J. Castaneda   J. Hung-Ming Chien Anand   S.B. Wu   S. Meng-An Pan Roofougaran   R. Hea Joung Kim Lettieri   P. Ibrahim   B. Rael   J.J. Tran   L.H. Geronaga   E. Yeh   H. Frost   T. Trachewsky   J. Rofougaran   A.
Affiliation:Broadcom Corp., Irvine, CA, USA;
Abstract:A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.
Keywords:
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