Fabrication of short channel MOSFETs with refractory metal gates using RF sputter etching

Fabrication of sub-μm p-channel MOSFETs with refractory metal gates using novel refinements of conventional photolithographic procedures is described. The method avoids the need for direct electron beam writing on the wafer and for ion implantation instead of diffusion. Autoregistration Mo gate structures down to 2 μm corresponding to an estimated channel length of 0 · 7 μm were made using RF sputter etching for the drain-source windows while masking with a positive photoresist. This was contact patterned using a chromium-on-glass mask made by electron beam writing and RF sputter etching. Sputter-deposited boron-doped SiO₂ was used as the diffusion source for the source-drain areas.The transistors were made on (100) phosphorus doped n-type silicon with an impurity concentration of 2 . 10¹⁶ cm^?3. Fabricated devices with channel lengths ≥ 1 · 7 μm had an apparent threshold voltage of 2·5 V (10 μA criterion) and for 1·7 μm channel length an apparent punch-through voltage of 18 V. A sputtered Mo layer ? 1 μm thick was used as gate material.A distinct advantage of using sputter etching with a single system capable of both deposition and etching is that it is possible to go directly to the next steps without exposure to air. These steps are mask removal in a partial H₂ and O₂ plasma, followed by further Argon sputter-etching and sputter deposition of a doped oxide diffusion source on the sputter-etched cleaned surface. This promises a better reproducibility of surface doping as there should be less oxide and less contamination than in conventional processes. The characteristics of the fabricated transistors did not indicate any un-annealable drift or gate oxide damage due to the presence of the plasma provided the Mo layer was sufficiently thick. Thus sputter etching which offers good resolution can be used in MOS fabrication.Due to its lower resistivity, Mo, which can be used an an additional interconnection layer (isolated from the A1 layer) offers better speed potential than Si, in certain types of circuits, e.g. high speed memories with long address lines.With a proper background doping of the wafer and diffusion time and temperature it was possible to obtain $\text{? 0 · 6 μm}$ lateral diffusion below the gate from both source and drain regions. It was thus possible to obtain sub-μm p-channel MOSFETs even while working close to the limits of normal optical contact production of micropatterns, which is 1–2 μm.