A simplified computer analysis for n-well guard ring efficiency in CMOS circuits

Based on solving the 2-D continuity and current transport equations for electrons injected into the substrate of a n-well CMOS, a quantitative evaluation of n-well guard ring efficiency in terms of the escape electron current is presented. Simulation results show that in the worst-case condition Auger recombination inherent in the heavily-doped substrate of epi-CMOS is responsible for the enhancement of n-well guard ring efficiency. Also, our simulations show that the substrate doping should be as high as possible and the epi-layer thickness should be as thin as possible. Thus a narrow well-type guard ring can be used in order to make efficient use of epi-CMOS for suppressing the escape electron current to a low level so as to preclude latch-up.