| 高精度计量芯片数字系统研究与设计 |
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| 引用本文： | 尹汝泼,李烨,袁世强.高精度计量芯片数字系统研究与设计[J].计算机工程与应用,2012,48(4):22-24. |
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| 作者姓名： | 尹汝泼 李烨 袁世强 |
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| 作者单位： | 1.无锡华润上华科技有限公司 智能产品平台，上海 2012032.上海理工大学 光电信息与计算机工程学院，上海 200093 |
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| 基金项目： | 国家自然科学基金（No.61074087）. |
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| 摘 要： | 从Full-chip设计角度出发，分析和提炼高精度计量芯片设计基本准则，研究相关的数字系统核心算法，优化RTL数字设计架构，使芯片不仅具有高精度，而且面积得到有效控制，为设计符合智能电表新标准的计量芯片提供重要参考。通过仿真、FPGA验证，表明芯片设计方法的有效性，该款芯片已成功流片。
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| 关 键 词： | 智能电表 数字计量单元 核心算法 RTL时钟复用 |
| 修稿时间： | |
Research and design of high precision smart metering digital IC |
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| YIN Rupo
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LI Ye
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YUAN Shiqiang.Research and design of high precision smart metering digital IC[J].Computer Engineering and Applications,2012,48(4):22-24. |
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| Authors: | YIN Rupo LI Ye YUAN Shiqiang |
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| Affiliation: | 1.Department of Smart Product Platform, CSMC, Shanghai 201203, China2.School of Optical-Electrical and Computer Engineering, University of Shanghai for Science and Technology, Shanghai 200093, China |
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| Abstract: | Thorough studies are performed on design principles for high precision energy measurement unit from the full chip design viewpoint. Based on the proposed kernel algorithms and optimized RTL clock reuse method, high performances as well as low cost are achieved. It can be used as an important reference for smart meter IC design satisfying the latest standards. Its efficiency is verified through simulation and FPGA demonstration. The chip has been taped out. |
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| Keywords: | smart meter digital energy measurement unit kernel algorithm RTL clock reuse |
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