| 基于FPGA的KLT特征点多层次归并排序 |
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| 引用本文： | 柴志雷,方万元.基于FPGA的KLT特征点多层次归并排序[J].计算机工程与应用,2014,50(21):157-161. |
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| 作者姓名： | 柴志雷 方万元 |
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| 作者单位： | 江南大学 物联网技术应用教育部工程研究中心，江苏 无锡 214122 |
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| 基金项目： | 国家自然科学基金(No.60703106，No.61170121，No.61202312)。 |
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| 摘 要： | KLT算法已在多个领域得到成功的应用，其中特征点的排序是用来选择好的特征点跟踪的关键。针对传统排序算法计算耗时、实时性差的缺点，提出一种可并行的多层次归并排序算法并在FPGA中实现了其并行计算，同时分析了其周期精确的计算时间。结果表明该归并排序算法可以O(N)]的时间复杂度完成特征点的排序，能够满足高清分辨率的图像/视频数据中KLT特征点排序的实时性要求。
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| 关 键 词： | 归并排序 KLT 现场可编程门阵列（FPGA）排序 |
FPGA-based multi-level parallel merge sorting architecture for KLT feature points |
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| CHAI Zhilei,FANG Wanyuan.FPGA-based multi-level parallel merge sorting architecture for KLT feature points[J].Computer Engineering and Applications,2014,50(21):157-161. |
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| Authors: | CHAI Zhilei FANG Wanyuan |
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| Affiliation: | Development Center of Internet of Things Engineering, MoE, Jiangnan University, Wuxi, Jiangsu 214122, China |
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| Abstract: | The Kanade-Lucas-Tomasi feature tracker（KLT）has received special attention due to its effectiveness on image track. The sort of feature point is the key point of joining the feature detection and feature track. This paper presents a novel FPGA-based parallel merge sort architecture for the KLT feature points, then analyzes its time period. The time complexity of the parallel merge sort architecture is O（N ） . The result shows that the FPGA-based merge sort can solve the real-time KLT feature points sort problem for HD image/video resolution. |
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| Keywords: | parallel merge sort Kanade-Lucas-Tomasi(KLT) Field Programmable Gate Array(FPGA)sort |
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