Circuit implications of gate oxide breakdown |
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| Authors: | J. H. Stathis, R. Rodrí guez,B. P. Linder |
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| Affiliation: | a IBM Research Division, P.O. Box 218, Yorktown Heights, NY 10598, USA;b Department d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193, Bellaterra, Spain |
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| Abstract: | A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains. |
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