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70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing
Authors:Ghafour Amouzad Mahdiraji  Mohamad Khazani Abdullah  Makhfudzah Mokhtar  Amin Malek Mohammadi  Ahmad Fauzi Abas  Safuraa Mohd Basir  Raja Syamsul Azmir Raja Abdullah
Affiliation:1.Department of Computer and Communication Systems Engineering,University Putra Malaysia,Serdang,Malaysia;2.Significant Technologies Sdn. Bhd.,Serdang,Malaysia
Abstract:The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively.
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