| 基于FPGA的移位寄存器流水线结构FFT处理器设计与实现 |
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| 引用本文： | 郝小龙,韦高,刘娜.基于FPGA的移位寄存器流水线结构FFT处理器设计与实现[J].现代电子技术,2010,33(9):172-176. |
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| 作者姓名： | 郝小龙 韦高 刘娜 |
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| 作者单位： | 西北工业大学,电子信息学院,陕西,西安,710129 |
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| 摘 要： | 设计实现了基于FPGA的256点定点FFT处理器。处理器以基-2算法为基础,通过采用高效的两路输入移位寄存器流水线结构,有效提高了碟形运算单元的运算效率,减少了寄存器资源的使用,提高了最大工作频率,增大了数据吞吐量,并且使得处理器具有良好的可扩展性。详细描述了具体设计的算法结构和各个模块的实现。设计采用Verilog HDL作为硬件描述语言,采用QuartusⅡ设计仿真工具进行设计、综合和仿真,仿真结果表明,处理器工作频率为72 MHz,是一种高效的FFT处理器IP核。
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| 关 键 词： | FFT处理器 流水线结构 FPGA QuartusⅡ Verilog HDL |
Design and Implementation on FFT Processor of FPGA-based Shift Register Pipelined Architecture |
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| HAO Xiao-long,WEI Gao,LIU Na.Design and Implementation on FFT Processor of FPGA-based Shift Register Pipelined Architecture[J].Modern Electronic Technique,2010,33(9):172-176. |
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| Authors: | HAO Xiao-long WEI Gao LIU Na |
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| Affiliation: | HAO Xiao-long,WEI Gao,LIU Na(School of Electronic , Information,Northwestern Polytechnical University,Xi\'an 710129,China) |
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| Abstract: | A 256 point FPGA-based fixed-point FFT processor is designed.The processor is based on radix-2 DIF algorithm.The operating efficiency of butterfly arithmetic union is enhanced,the use of register is redaced and the maximum operating frequency is improved and the data throughput is enhanced by adopting an efficient shift register pipelined architecture.The designed FFT processor also has good scalability.The algorithm architecture and the realization of each module are described in detail.The design uses Ver... |
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| Keywords: | FPGA Verilog HDL |
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