| 32位嵌入式RISC处理器的VLSI实现 |
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| 引用本文： | 徐科,王文婷,闵昊. 32位嵌入式RISC处理器的VLSI实现[J]. 半导体技术, 2003, 28(12): 57-62 |
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| 作者姓名： | 徐科 王文婷 闵昊 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海200433 |
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| 基金项目： | This work is supported by the National863 Plan of China(2002AA1Z1060) |
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| 摘 要： | 本文实现了一个低功耗,高速度的32位RISC处理器。芯片采用了ARM V4的指令集,哈佛结构和五级流水线。同时利用了改进的流水冲突检测控制和异常处理使得流水线能以较高的速度顺序流动。与商用的ARM7TDMI相比,在0.6mm的工艺上达到了与商用0.35mm工艺制造相同的速度,同时CPI降低了26%,MIPS上升了36%。整个系统在APTIX公司提供的MP3CF硬件仿真器上完成了硬件验证,现已完成了版图设计并提交流片。
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| 关 键 词： | RISC 哈佛结构 流水线 CPI MIPS |
| 文章编号： | 1003-353X(2003)12-0057-06 |
| 修稿时间： | 2002-12-03 |
VLSI implementation of a 32bit embedded reduced-instruction-set-computer |
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| XU Ke,WANG Wen-Ting,MIN Hao. VLSI implementation of a 32bit embedded reduced-instruction-set-computer[J]. Semiconductor Technology, 2003, 28(12): 57-62 |
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| Authors: | XU Ke WANG Wen-Ting MIN Hao |
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| Abstract: | A 32bit embedded RISC microprocessor designed for low-power, low-cost and high-speed is described. The chip implements the ARM V4 instruction set. Based on ARM7TDMIframework, this microprocessor takes the advantage of Harvard architecture and implements a 5-stage pipeline. It also utilizes the improved pipeline hazard control and exception handle circuit forthe fluent flow of pipeline. Compared with commercial ARM7TDMI implemented on 0.35mm CMOSprocess, the chip can achieve the same speed on 0.6mm CMOS process, while the CPI decreases 26%,MIPS increases 36%. The whole design has been tested successfully under Aptix System ExplorerMP3CF hardware verification platform and taped out on CSMC 0.6mm CMOS process. |
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| Keywords: | RISC Harvard architecture pipeline CPI MIPS |
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