64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-nslatency |
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| Authors: | Heald R. Shin K. Reddy V. I-Feng Kao Khan M. Lynch W.L. Lauterbach G. Petolino J. |
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| Affiliation: | Sun Microelectron., Palo Alto, CA; |
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| Abstract: | Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way set-associative cache. This address adder avoids time-consuming carry propagation by using an A+B=K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-μm process, This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access |
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