| FSA乘法器的设计与实现 |
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| 引用本文： | 商丽卫,刘耀军. FSA乘法器的设计与实现[J]. 电脑开发与应用, 2012, 25(4): 21-23 |
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| 作者姓名： | 商丽卫 刘耀军 |
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| 作者单位： | 1. 太原科技大学计算机科学与技术学院,太原,030024
2. 太原师范学院,太原,030012 |
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| 基金项目： | 山西省重点建设学科专项基金资助项目(20101029) |
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| 摘 要： | 鉴于有限状态机对于具有逻辑顺序和时序规律的事件能有清晰的描述,对传统乘法器设计进行改进。提出一种快速、低功耗的FSA乘法器设计。该设计使用VHDL语言进行实现,并在QuartusⅡ上通过了仿真。仿真结果表明基于状态机的与基于逻辑电路的设计相比,在运算过程中产生的功耗以及运算速度上有较大的改善。
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| 关 键 词： | 有限状态机 FSA乘法器 VHDL Quartus |
The Design and Implementation of FSA Multiplier |
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| SHANG Li-wei , LIU Yao-jun. The Design and Implementation of FSA Multiplier[J]. Computer Development & Applications, 2012, 25(4): 21-23 |
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| Authors: | SHANG Li-wei LIU Yao-jun |
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| Affiliation: | 1. Computer Science and Technology School, Taiyuan University of Science and Technology, Taiyuan 030024, China, 2. Taiyuan Normal University, Taiyuan 030012 ,China) |
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| Abstract: | Based on the traditional multiplier, a kind of high-speed and low-power FSA multiplier was proposed. The finite state automaton was introduced to design the multiplier, because it can clearly describe the events with a logic and timing sequence. The programming language-VHDL was used to achieve this design which was simulated in Quartus I ~ The simulation result shows that the design based on the finite state automaton has a better performance in power and speed compared to the design based on the logic circuit. |
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| Keywords: | finite state automaton FSA multiplier VHDL quartus |
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