Verification of saturation velocity lowering in MOSFET's inversionlayer |
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Authors: | Shigyo N Shimane T Suda M Enda T Fukuda S |
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Affiliation: | Microelectron. Eng. Lab., Toshiba Corp., Yokohama ; |
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Abstract: | With reduction of the MOSFET's channel length L, the drain saturation current of MOSFET's is determined by the saturation velocity vsat in the inversion layer. Hence, the modeling of vsat becomes very important. In this paper, vsat in the inversion layer has been examined by using simulation experiment. New parameter values for vsat model in the inversion layer are proposed. In order to verify the vsat model, the impurity profiles of MOSFET's are calibrated to fit the threshold voltage Vth-L characteristics. Then, we validate new vsat model by comparing the experiments of ID-VD characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM) |
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