基于VHDL语言的参数化设计方法

随着FPGA制造工艺的不断进步，越来越多的应用可以在FPGA中实现。虽然用于FPGA设计的VHDL语言具有很好的可移植性，但是FPGA芯片的可用资源不尽相同，因此对设计的规模进行参数化才能实现设计的可移植及充分利用FPGA的资源。此外，同一算法在不同的应用领域中，也会需要对其规模进行改变。设计的参数化是指只需要对参数进行设定就可以自动生成相应规模设计的技术。首先提出了一种基于综合工具的VHDL参数化设计方法，其次以多路奇偶校验生成器为例，详细说明了参数化的基本过程，最后在HMMer的FPGA实现中应用所提出的方法，从而实现对运算单元数量的控制。所提出的参数化方法具有操作简单、代码变动小、无需要第三方代码支持等优点。实验表明，该方法是VHDL设计中成本小、效果好的参数化设计方案。

VHDL based design parameterization methodology

With the fast development of FPGA manufacture technology, more and more algorithms can be implemented on FPGA.Although VHDL has its own portability, a design＇s portability acquires the management of scale with specify FPGA chip.Besides one kind of algorithm can be applied to many areas ,the size of design should be adaptive to particular application.Design parameterization is a design method that can generate designs of various processing capability by corresponded parameters.Design parameterization is an efficient way for portability.This paper firstly proposes a synthesis tool based param-eterization method on VHDL, secondly illustrates detail operations with design of a multi-way parity checksum generator, and finally applies the parameterization technique onto a FPGA implementation of HMMer.The parameterization method proposed by this paper has simple operations, minimal code change, and no dependency to executable code generators.Experiment shows that it is a low cost but highly efficient parameterization solution.