| 深亚微米SOC芯片分层设计方法 |
| |
| 引用本文： | 刘德启,胡忠. 深亚微米SOC芯片分层设计方法[J]. 半导体技术, 2007, 32(4): 335-338 |
| |
| 作者姓名： | 刘德启 胡忠 |
| |
| 作者单位： | 上海交通大学,电子工程学院,上海,200030 |
| |
| 摘 要： | 根据深亚微米SOC设计的特点和需求,提出了一种新的基于模块的全芯片分层设计方法,它把系统架构、逻辑设计以及物理实现有机结合到一起.通过渐进式时序收敛完成芯片的层次规划,并最终达到一次实现芯片级的时序收敛,大大提高了深亚微米SOC设计的效率,并在实际设计之中得到了有效验证.
|
| 关 键 词： | 深亚微米 片上系统 分层 渐进收敛 |
| 文章编号： | 1003-353(2007)04-335-04 |
| 修稿时间： | 2006-12-05 |
Hierarchical Design Solution for Deep Submicron SOC Chip |
| |
| LIU De-qi,HU Zhong. Hierarchical Design Solution for Deep Submicron SOC Chip[J]. Semiconductor Technology, 2007, 32(4): 335-338 |
| |
| Authors: | LIU De-qi HU Zhong |
| |
| Affiliation: | School of Electronic Engineering, Shanghai Jiao Tong University,Shanghai 200030,China |
| |
| Abstract: | After analyzing characteristic and design requirement deep submicron SOC,a new complete,full-chip,hierarchical design solution was proposed.System architecture,logical design and physical implementation were integrated perfectly.Progressive timing refinement was used to drive hierarchical planning for SOC.Finally the full-chip timing closure was met one pass.And the design efficiency for deep sub micro SOC would be improved greatly.And the solution was successfully applied to SOC design in practice. |
| |
| Keywords: | deep submicron SOC hierarchical progressive refinement |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
