Corner turn of SAR data based on multi-FPGAs parallel system

A segmented storage strategy is provided for corner turn of Synthetic Aperture Radar (SAR) data based on multiple Field-Programable Gate Arrays (multi-FPGAs) parallel system. The optimal segmented length is related to the type of the Double-Data-Rate (DDR) memory. Address mapping between pixel location and memory location is expressed in pseudo-code, and the address mapping between bus address and memory address is also deduced in universal expression. A hardware module is given to implement DDR2 SDRAM controller. Practical debugging and experiment have proved that the segmented storage method balances the access rate between row and column in memory cells and accelerates the corner turn of two dimensional image data. Compared with previous related works, our implementation could get higher Throughput/Area and provide much more optimal performance.