An experimental 256-Mb DRAM with boosted sense-ground scheme |
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Authors: | Asakura M Ooishi T Tsukude M Tomishima S Eimori T Hidaka H Ohno Y Arimoto K Fujishima K Nishimura T Yoshihara T |
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Affiliation: | ULSI Lab., Mitsubishi Electr. Corp., Hyogo; |
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Abstract: | In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time |
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