基于并行流水线结构的可重配FIR滤波器的FPGA实现

数字信号处理,常常是计算密集和高性能需求的。FIR滤波器由于其稳定和简单,在数字信号处理中常被采用。随着实时性和低成本要求的提高,对FIR滤波器的要求也越来越高。单一的流水结构和并行FIR结构都不能很好地满足实现性要求。因此,在这里提出一种用于FPGA实现的并行流水结构的FIR滤波器的实现方案。

FPGA Implementation of Reconfigurable FIR Filter Based on Parallel Pipeline Structure

DSP,which is compute intensive and typically need high performance.FIR filter is a stabilized and simple structured filter,so it is used usually.As the need of real-time processing is becoming more and more important,the FIR filter using only pipeline technology may not satisfy the needing.On the other hand,the all parallel structured FIR filter need so much many die area.So a new implementation of FIR is given here.