Evolutionary circuit design for fast FPGA-based classification of network application protocols |
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| Affiliation: | 1. Department of Computer Architecture and Computer Technology and CITIC-UGR, University of Granada, Granada, Spain;2. LaSEEB-ISR-IST, Technical University of Lisbon (IST), Lisbon, Portugal;1. BORDA Research Unit and Multidisciplinary Institute of Enterprise (IME), Universidad de Salamanca, 37007 Salamanca, Spain;2. Department of Economics and Business, Universidad de Almería, 04120 Almería, Spain;1. Department of Applied Mathematics and Computer Science, Ghent University, Belgium;2. Affectv Limited, London, United Kingdom;3. Department of Computer Science and AI, Research Center on Information and Communications Technology (CITIC-UGR), University of Granada, Spain;4. Department of Information Systems, Faculty of Computing and Information Technology, King Abdulaziz University, Jeddah, Saudi Arabia;1. CAS Key Laboratory of Technology in Geo-spatial Information Processing and Application Systems, University of Science and Technology of China, Hefei, China;2. USTC-Birmingham Joint Research Institute in Intelligent Computation and Its Applications (UBRI), University of Science and Technology of China, Hefei, China;1. Department of Electrical Engineering, COMSATS Institute of Information Technology, Attock, Pakistan;2. Hamdard Institute of Information Technology, Hamdard University, Islamabad, Pakistan;3. Department of Electronic Engineering, International Islamic University, Islamabad, Pakistan;4. Department of Mathematics, Imam Khomeini International University, Qazvin, 34149-16818, Iran |
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| Abstract: | The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols. |
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| Keywords: | Application protocol Classifier Cartesian genetic programming Field programmable gate array |
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