| 高速低抖动时钟稳定电路设计 |
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| 引用本文： | 陈红梅,邓红辉,张明文,陶阳,尹勇生. 高速低抖动时钟稳定电路设计[J]. 电子测量与仪器学报, 2011, 25(11): 966-971. DOI: 10.3724/SP.J.1187.2011.00966 |
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| 作者姓名： | 陈红梅 邓红辉 张明文 陶阳 尹勇生 |
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| 作者单位： | 1. 合肥工业大学微电子所,合肥,230009
2. 湖南大学电气与信息工程学院,长沙,410100 |
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| 基金项目： | 国家自然科学基金面上项目 |
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| 摘 要： | 基于0.18 μm CMOS Mixed Signal工艺,设计实现了用于高速ADC的低抖动时钟稳定电路.在传统延迟锁相环结构(DLL)时钟电路研究基础上进行改进:设计基于RS锁存器的新型鉴相器,消除传统鉴相器相位误差积累效应；采用连续时间积分器取代电荷泵进行时钟占空比检测,减小由于电荷泵充放电电流不一致而导致的误差....
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| 关 键 词： | 高速模数转换器 延迟锁相环 占空比调整电路 连续积分器 时钟抖动 |
Design of high-speed low-jitter clock stabilizer circuit |
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| Chen Hongmei,Deng Honghui,Zhang Mingwen,Tao Yang,Yin Yongsheng. Design of high-speed low-jitter clock stabilizer circuit[J]. Journal of Electronic Measurement and Instrument, 2011, 25(11): 966-971. DOI: 10.3724/SP.J.1187.2011.00966 |
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| Authors: | Chen Hongmei Deng Honghui Zhang Mingwen Tao Yang Yin Yongsheng |
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| Affiliation: | 1(1.Institute of VLSI Design,Hefei University of Technology,Hefei 230009,China; 2.College of Electrical and Information Engineering,Hunan University,Changsha 410100,China) |
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| Abstract: | Based on 0.18 μm CMOS mixed signal process,a high-precise clock stabilizer circuit for high-speed ADC was presented.A double-edge triggered RS latch phase detector was designed to eliminate the effect of the accumulation phase of traditional phase detector.A continuous time integrator was utilized to test the clock duty cycle and control the rising edge of an inverter,which reduced the charge and discharge current inconsistent errors of the charge pump.The chip area is about 0.339 mm×0.314 mm.The post-simulation results show that the circuit can adjust output clock duty cycles to(50±0.15)% with 10%~90% input duty cycle from 20~150 MHz in less than 100 ns,and the measurement jitter is 0.00127 ps at 150 MHz.Therefore it can satisfy the clock requirement of high-performance ADC. |
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| Keywords: | high-speed ADC delay locked loop duty cycle stabilizer continuous time integrator clock jitter |
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