A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit insilicon bipolar technology |
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Authors: | Soyuer M. |
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Affiliation: | IBM Thomas J. Watson Res. Center, Yorktown Heights, NY; |
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Abstract: | A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 223-1 pseudorandom bit sequence |
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