Degradation mechanism for silicon p+-n junctions under forward bias |
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Authors: | RW Hamaker ZC Putney RL Ayers PH Smith |
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Affiliation: | IBM Corporation, Manassas, Virginia, U.S.A. |
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Abstract: | Leakage current degradation has been observed during forward bias stressing of silicon integrated p+-n junctions. Detailed characterization results of the anomalous leakage behavior are discussed in this paper. From these results an electric field-enhanced impurity diffusion mechanism has been proposed to explain both the strong temperature and forward bias dependencies on leakage current time-to-saturation. An activation energy has been determined for this mechanism (0.48±0.04 eV) and is in good agreement with that previously determined for diffusion of interstitial copper in p-type silicon. Subsequent Secondary Ion Mass Spectrometer elemental analysis has confirmed the presence of copper near the surface of the epitaxial layer containing the p+-n device. |
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