A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs) |
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| Affiliation: | 1. Department of Electronics and Communication, Ain Shams University, Cairo, Egypt;2. Center of Nanoelectronics and Devices at Zewail City of Science and Technology/AUC, Cairo, Egypt;1. Department of Electrical Engineering and Information Technology, University Federico II, 80125 Naples, Italy;2. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, I-20133 Milan, Italy;3. Infineon Technologies AG, Neubiberg 85579, Germany;1. Thales Corporate Engineering, 19-21 avenue Morane Saulnier, 78140 Vélizy-Villacoublay, France;2. Université Paris Ouest, Laboratoire Thermique Interfaces Environnement (LTIE), EA 4415, 50 rue de Sèvres, 92410 Ville d''Avray, France;3. Université Paris XIII, Sorbonne Paris Cité, 93430 Villetaneuse, France;4. Ecole Nationale Supérieure d''Electricité et de Mécanique de Nancy, 2 Avenue de la Forêt de Haye, 54500 Vand?uvre-lès-Nancy, France;1. Department of Electronics and Information Systems, University of Ghent, Sint Pietersnieuwstraat 41, 9000 Ghent, Belgium;2. Department of Microelectronics and Computer Science, Lodz University of Technology, Wolczanska 221/223, 90-924 Lodz, Poland;1. National Institute for Astrophysics, Optics and Electronics-INAOE, Mexico;2. Pontifical Catholic University of Rio Grande do Sul-PUCRS, Brazil |
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| Abstract: | In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (Vd). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz. |
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