Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop |
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| Affiliation: | 1. School of Materials Science and Engineering, Nanyang Technological University, Singapore 639798, Singapore;2. CNES, French Space Agency, 18 Avenue Edouard Belin, Toulouse 31401, France;3. Temasek Laboratories@NTU, Nanyang Technological University, Singapore 637553, Singapore;1. IM2NP-UMR7334, Polytech''Marseille, Aix-Marseille University, CNRS, Marseille, France;1. Institut Télécom/Télécom ParisTech, CNRS-LTCI UMR 5141, Paris, France;2. Center for computional science, Federal University of Rio Grande, Rio Grande, Brazil;1. Science and Technology on Integrated Logistics Support Laboratory, National University of Defense Technology, Changsha, China;2. Mianyang High-tech Experimental Middle School, Mianyang, China |
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| Abstract: | A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy. Post-processing of the data from the laser mapping facilitated the plotting of the cross-section versus laser energy curve. We found a clear shift in the cross-section curves after voltage stress of 130 h. Comparisons of data revealed at least a doubled increase in sensitive areas after voltage stress. During the voltage stress, various electrical parameters were monitored and changes were observed. It was found that the increase in SEU sensitivity is related to electrical parameter changes and SPICE simulation results concur likewise. |
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