The effect of annealing temperature on the electronic parameters and carrier transport mechanism of Pt/n-type Ge Schottky diode |
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| Affiliation: | 1. Department of Physics, College of Science, Shanghai University, Shanghai 200444, China;2. Department of Materials Science and Engineering, Shanghai University, Shanghai 200072, China;3. Department of Chemistry, College of Sciences, Shanghai University, Shanghai 200444, China;4. Institute of NanoMicroEnergy, Shanghai University, Shanghai 200444, China;5. Shanghai Key laboratory of High Temperature Superconductors, China;1. Department of Physics, Mepco Schlenk Engineering College, Sivakasi 626 005, Tamil Nadu, India;2. Department of Chemistry, Mepco Schlenk Engineering College, Sivakasi– 626 005, Tamil Nadu, India |
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| Abstract: | The Pt nano-film Schottky diodes on Ge substrate have been fabricated to investigate the effect of annealing temperature on the characteristics of the device. The germanide phase between Pt nano-films and Ge substrate changed and generated interface layer PtGe at 573 K and 673 K, Pt2Ge3 at 773 K. The current–voltage(I - V) characteristics of Pt/n-Ge Schottky diodes were measured in the temperature range of 183–303 K. Evaluation of the I - V data has revealed an increase of zero-bias barrier height ΦB0 but the decrease of ideality factor n with the increase in temperature. Such behaviors have been successfully modeled on the basis of the thermionic emission mechanism by assuming the presence of Gaussian distributions. The variation of electronic transport properties of these Schottky diodes has been inferred to be attributed to combined effects of interfacial reaction and phase transformation during the annealing process. Therefore, the control of Schottky barrier height at metal/Ge interface is important to realize high performance Ge-based CMOS devices. |
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