A transient noise simulation model for the analysis of the optimal number of stages of the analog accumulator in TDI CMOS image sensors |
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| Affiliation: | 1. Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama 226-8502, Japan;2. Tokyo City University, Tokyo 158-8557, Japan;1. TU Wien, Institute of Sensor and Actuator Systems, Floragasse 7, 1040 Vienna, Austria;2. Happy Plating GmbH, Viktor-Kaplan-Straße 2C, 2700 Wiener Neustadt, Austria;3. Friedrich-Alexander-University Erlangen-Nuremberg, Institute for Electronics Engineering, Cauerstr. 9, D-91058 Erlangen, Germany |
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| Abstract: | In this paper, a fast transient noise simulation model is proposed to analyze the optimal number of stages for the maximum signal to noise ratio (SNR) of the analog accumulator in a fixed silicon area. The Transient Noise Simulation (TNS) is required to confirm the analysis of the optimal number of stages, which requires long simulation time. In order to accelerate our analysis, a fast transient noise simulation model (TNSM) is proposed based on the noise analysis and shown to be effective by TNS. Numerical analysis is verified by the TNSM, and it indicates that the optimal number of stages in a fixed area changes with the noise of the input signal. |
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