Off-state degradation with ac bias in PMOSFET |
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| Affiliation: | 1. DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd, 1, Samsungjeonja-ro, Banwol-Dong, Hwaseong-si, Gyeonggi-do 445-701, Republic of Korea;2. College of Information and Communication Engineering, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon-si, Gyeonggi-do 440-746, Republic of Korea;1. Department of Mechanical Engineering, Nan Kai University of Technology, Taiwan;2. Graduate Institute of Precision Engineering, National Chung Hsing University, Taichung 402, Taiwan;1. Department of ECE, Sri Sivasubramaniya Nadar (SSN) College of Engineering, Kalavakkam 603110, Tamil Nadu, India;2. Department of IT, Sri Sivasubramaniya Nadar (SSN) College of Engineering, Kalavakkam 603110, Tamil Nadu, India;1. National Research Tomsk Polytechnic University, Russia;2. Research Institute of Semiconductor Devices, Russia |
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| Abstract: | For the first time, the current failure of p-channel MOSFETs used for the sub-wordline driver of state-of-the-art DRAM chips was investigated during off-state switching cycles. With increasing switching speed for the sub-wordline driver, the subthreshold leakage current of p-channel MOSFETs increased, and resulted in serious stand-by current failure. The model proposed in this work suggested that the off-state degradation of p-channel MOSFETs with ac bias will intensify as the dimensions of devices decrease due to both the high electric field and the high operating frequency. The roles of various device parameters- such as gate length, gate-tab width, doping concentration at the source/drain extensions, operating temperature and operating frequency- on the degradation of p-channel MOSFETs were investigated. |
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