Thermo-mechanical simulation of PCB with embedded components |
| |
| Affiliation: | 1. Université de Lorraine, LEM3 Laboratoire d''Etude des Microstructures et de Mécanique des Matériaux, UMR CNRS 7239, Ile du Saulcy, 57045, Metz, France;2. CIMULEC, ZI Les Jonquières, 57365 Ennery, France;3. Thales Global Services, 19/21 av. Morane Saulnier, 78140, Vélizy-Villacoublay, France;1. Shanghai Key Laboratory of Multidimensional Information Processing, Department of Electrical Engineering, East China Normal University, Shanghai, 200241;2. Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China;1. School of Electrical and Computer Engineering, University of Tehran, College of Engineering, Tehran, Iran;2. Department of Electrical and Computer Engineering, San Francisco State University, CA, USA;1. Microelectronics Research, Group Faculty of Information Technology and Electrical Engineering, University of Oulu, 90014, Finland;2. Tampere University of Applied Sciences, Finland;3. Electronics and Communications Engineering, Tampere University of Technology, Finland;1. Department of Mechanical Engineering, Nan Kai University of Technology, Taiwan;2. Graduate Institute of Precision Engineering, National Chung Hsing University, Taichung 402, Taiwan |
| |
| Abstract: | In recent years, in order to increase density and performance of electronic boards, components are embedded in internal layers of printed circuit boards (PCBs). The reliability of this new technology has to be investigated to ensure the working of the electronic boards submitted to harsh environment and long mission profiles. To study the thermo-mechanical behavior of these boards, finite element simulations have been performed. It is observed that embedded passive chips are subjected to complex loading during the lamination process, due mostly to shrinkage of the resin, differences in material properties and also because of temperature excursion. The effects of material parameters and of the geometrical configuration are investigated in details. It will be shown that the generated stresses are not critical for the passive chip size considered in the present work. |
| |
| Keywords: | |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
