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Degradation of pMOSFETs due to hot electron induced punchthrough
Affiliation:1. Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 790-784, Republic of Korea;2. Memory Division, Samsung Electronics, Hwasung, Gyeonggi 445-701, Republic of Korea;1. ECS, University of Southampton, Southampton, UK;2. Dept. of Engineering, University of Westminster, London, UK
Abstract:This paper proposes a method which can separate the parasitic effect from the drain current Id vs. gate voltage Vg curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An Id vs. Vg curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of Id vs. channel width W at each Vg to W = 0 μm. The Id vs. Vg curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage Vth of the parasitic MOSFET but increased Vth of the main MOSFET. These two opposite behaviors of Vth resulted in little HEIP-induced shift of Vth at W = 2.5 μm. | Vd | to secure ten-year HEIP lifetime of 10% shift of Vth was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.
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