A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination |
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Authors: | P Vijaya Sankara Rao Nachiket Desai Pradip Mandal |
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Affiliation: | (1) Department of Electronic Engineering, Feng Chia University, 100, Wenhwa Rd, Seatwen, Taichung, Taiwan, 40724, ROC |
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Abstract: | In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption
is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with
a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate
the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver
selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal.
For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current
to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric
impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main
driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology.
Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target
BER of 10−15, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination
producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm
1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW. |
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