A single-chip MPEG-2 codec based on customizable media embedded processor |
| |
| Authors: | Ishiwata S Yamakage T Tsuboi Y Shimazawa T Kitazawa T Michinaka S Yahagi K Takeda H Oue A Kodama T Matsumoto N Kamei T Saito M Miyamori T Ootomo G Matsui M |
| |
| Affiliation: | SoC R&D Center, Toshiba Corp., Kawasaki, Japan; |
| |
| Abstract: | A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time. |
| |
| Keywords: | |
|
|
