Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance