| 基于FPGA的F-RAM防掉电设计 |
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| 引用本文： | 任泽宇,郭鹏程,王建超,罗丁利.基于FPGA的F-RAM防掉电设计[J].电子科技,2014,27(7):89-92. |
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| 作者姓名： | 任泽宇 郭鹏程 王建超 罗丁利 |
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| 作者单位： | (北方通用电子集团有限公司 数字工程部,陕西 西安 710100) |
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| 摘 要： | 在复杂实验条件下,需采用非易失性铁电存储器记录重要数据。为防止二次上电时实验数据被覆盖,需设计防掉电功能。文中介绍了一种F-RAM的防掉电设计思路,并基于现场可编程门阵列实现,板级验证工作正常,并已在相关项目中得到应用且达到了预期功能。
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| 关 键 词： | 非易失铁电存储器 防掉电 现场可编程门阵列 |
Power Down Protection Design for F-RAM Based on FPGA |
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| REN Zeyu,GUO Pengcheng,WANG Jianchao,LUO Dingli.Power Down Protection Design for F-RAM Based on FPGA[J].Electronic Science and Technology,2014,27(7):89-92. |
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| Authors: | REN Zeyu GUO Pengcheng WANG Jianchao LUO Dingli |
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| Affiliation: | (Department of Digital Engineering,North General Electronics Group Co.,Ltd,Xi'an 710100,China) |
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| Abstract: | The F-RAM is required to record important data in experiments under complex conditions. The power down protection function is necessary to prevent the already valid data from being covered on secondary electricity. A design of a power down protection is introduced and realized on FPGA. The design works well on board, and realizes the expected function in related project applications. |
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| Keywords: | ferroelectric nonvolatile ram power down protection field programmable gate array |
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