CMOS circuit optimization |
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Authors: | Akira Kanuma |
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Affiliation: | Semiconductor Device Engineering Laboratory, Toshiba Corporation, 1-Komukai Toshiba-cho, Saiwai-ku, Kawasaki, Japan 210 |
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Abstract: | In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint. The propagation delay time for a CMOS in erter is calculated for a step function input. A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction. |
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